1. Field of the Invention
This disclosure relates to the field of data processing systems. More particularly, this disclosure relates to the arbitration of priority levels between interrupt signals.
2. Description of the Prior Art
It is known to provide data processing systems with interrupt controllers responsive to multiple interrupt signals each having an associated priority level. Arbitration mechanisms are provided such that when more than one interrupt signal is asserted at a given time, then the highest priority interrupt signal may be identified and used to trigger its associated interrupt processing ahead of the one or more pending interrupts having a lower priority value.
The priority levels associated with different interrupt signals may be fine-grained and potentially programmable. The priority levels may be represented by multi-bit numbers which are compared during arbitration in order to determine which priority level is highest. The arbitration between priority levels should be performed quickly in order to reduce interrupt latency. Interrupt latency is an important performance parameter, particularly in real time processing systems. Accordingly, the comparison of priority levels may be performed in hardware and with multiple comparisons being performed in parallel.